1. Field of the Invention
The present invention relates to a simulation circuit pattern evaluation method for evaluating a simulation circuit pattern which simulates a circuit pattern of a semiconductor integrated circuit, a manufacturing method of the semiconductor integrated circuit for manufacturing the semiconductor integrated circuit by evaluating the simulation circuit pattern, a test substrate having an aggregate of the simulation circuit patterns, and a test substrate group which is composed of a plurality of the test substrates.
2. Description of the Related Art
Conventionally, as a preliminary step to a commercialization of a semiconductor integrated circuit, a simulation circuit pattern or the like is formed and a performance test of elements, an optimization of process conditions or the like is performed, in order to improve the yield (for example, refer to Japanese Patent Laid-open Application No. 2001-44285).
Currently, in an optimization of a process condition for a wiring formation process, regular simulation wiring patterns are respectively formed with different process conditions on plural semiconductor wafers for testing (hereinafter, referred to as a “test wafer”), and these simulation wiring patterns are evaluated to thereby detect optimum process conditions.
Further, aggregates of simulation wiring patterns which mainly have reference states are respectively formed with different process conditions on plural test wafers, and the aggregates of these simulation wiring patterns are evaluated to thereby detect the optimum process conditions. Here, the aggregates of the simulation wiring patterns which mainly have the reference states are formed by combining plural parameters having two or three states as shown in Table 1, but they are formed to have the number of appearances of the reference states to be the maximum. Incidentally, in Table 1, the reference state for a “first layer wiring formation width” is “0.3 μm,” for a “first layer wiring formation length” is “20 μm,” for a “second layer wiring formation width” is “0.3 μm,” for a “second layer wiring formation length” is “20 μm,” for a “via hole formation position” is “center position,” and for a “via hole miss-alignment” is “0 (zero).”
TABLE 1ABCDEFGNo. 1 0.3 μm20 μm0.3 μm20 μmCenter0No. 2 0.3 μm100 μm 0.3 μm20 μmCenter0No. 3 0.3 μm200 μm 0.3 μm20 μmCenter0No. 4 0.3 μm20 μm1.0 μm20 μmCenter0No. 5 0.3 μm20 μm5.0 μm20 μmCenter0No. 6 0.3 μm20 μm0.3 μm100 μm Center0No. 7 0.3 μm20 μm0.3 μm200 μm Center0No. 8 0.3 μm20 μm0.3 μm20 μmEnd0No. 9 0.3 μm20 μm0.3 μm20 μmEnd10 No. 100.3 μm20 μm0.3 μm20 μmEnd30 No. 111.0 μm20 μm0.3 μm20 μmCenter0No. 121.0 μm100 μm 0.3 μm20 μmCenter0No. 131.0 μm200 μm 0.3 μm20 μmCenter0No. 141.0 μm20 μm1.0 μm20 μmCenter0No. 151.0 μm20 μm5.0 μm20 μmCenter0No. 161.0 μm20 μm0.3 μm100 μm Center0No. 171.0 μm20 μm0.3 μm200 μm Center0No. 185.0 μm20 μm0.3 μm20 μmCenter0A: Simulation wiring patter;B: First layer wiring formation width;C: First layer wiring formation length;D: Second layer wiring formation width;E: Second layer wiring formation length;F: Via hole formation position;G: Via hole miss-alignment
However, even in a case that an actual semiconductor integrated circuit is formed with optimum process conditions which are detected by a technique similar to the above-mentioned one, there is a problem of ineffectiveness in improving the yield. This problem is possibly caused by the fact that, when detected process conditions are suitable for some of the wiring patterns, they may not be suitable for the other wiring patterns since wiring patterns in various shapes exist on a semiconductor integrated circuit to be actually commercialized. Accordingly, it is conceivable to form an aggregate of simulation wiring patterns which simulate all the wiring patterns used for the semiconductor integrated circuit. However, the formation of the aggregate of the simulation wiring patterns which simulate all the wiring patterns results in numerous simulation wiring patterns, and thus it is impractical.